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power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 1 / 12 in-plug ? series: IPS20 and ips21 precision feedback controllers fixed and ptat references r r e e v v 5 5 introduction description in-plug ? IPS20 & ips21 integrated circuits are low-voltage current sensing feedback controllers used in switch mode power supplies to control load-side current and voltage. they have been designed to limit the power dissipated in the sensing circuitry for high output current applications that require current limiting. they also provide excellent loop stability and superb transient response. they both incorporate a 4v shunt regulator for maximum flexibility to power the chip. the IPS20 and ips21 only differ by the characteristics of the current sensing references. the IPS20 incorporates a trimmed 54mv reference with a positive temperature coefficient which closely matches that of a pcb copper trace. this copper trace sensing method can be used inexpensively with very low associated power losses. the ips21 incorporates a temperature compensated 100mv reference for more conventional resistors. both controllers feature the same voltage regulator section with a trimmed temperature stable voltage reference of 1.19v. this allows the output voltage of the smps to be set to any value down to about 1.2v. the IPS20 and ips21 are suitable for any smps and any make of smps controllers, including flyback, forward, pfc and dc/dc solutions. these flyback controllers work best in complement with the in-plug ? family of ips1x flyback controllers, ips10x pfc cont rollers and IPS20x push- pull controllers. features ? dual precision regulators for smps voltage and current control ? output currents up to 50a ? output voltage down to 1.2v ? 54mv or 100mv current sensing voltage ? 1.19v voltage reference ? operates with grounded optocoupler ? 4v shunt regulator for vcc supply applications ? fast chargers for power tools and other applications ? battery eliminators ? industrial and bench-type power supplies ? distributed power systems pin configuration: dip-8 / soic-8 ordering information for part number, packaging, and ordering information, please refer to the second-to-last page of this datasheet. vcc out (-) is vs vcomp opto gnd IPS20 ips21 1 45 8 icomp
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 2 / 12 functional block diagram pin description pin description 1- vcc ic positive supply pin. the chip behaves like a 4 volt zener diode referenced to gnd 2- vs voltage sensing pin. this is the inverting input of the voltage error amp lifier. the positive input of the amplifier is connected to an internal trimmed 1.20v voltage reference. an external voltage divider connected to this point sets the output voltage. this pin is also used for voltage loop compensation when required. 3- vcomp voltage loop compensation pin. this is the output of the voltage error amplifier. the voltage loop compensation network, when required, is connected between this point and vs pin. please note that this pin is not a zero-impedance node (1k nominal). 4- opto optocoupler driver pin. this pin drives and external optocoupler connected to gnd. a current-mode drive is used for maximum noise rejection. 5- icomp current loop compensation pin. (similar to vcomp) this is the output of the current error amplifier. the current loop compensation network, when required, is connected between this point and the is pin. please note that this is not a zero-impedance point (1k nominal). 6- is current sensing pin. this pin is the inverting input of the current sense amplifier. the positive input of the amplifier is connected to an internal trimmed reference. th e sensing threshold is 50mv ptat (IPS20) or 100mv constant (ips21). this pin should be connected through a resistor to the external current sensing resistor. 7- out (-) negative output pin. this pin is the negative side of the 1.20v trimmed voltage reference. it should be connected to the negative output of the smps. 8- gnd ground pin. this is the most negative ic pin. the first output decoupling capacitor should return to it. do not confuse this pin with the is pin and the out(-) pin which are described above. is vs opto vcomp trimmed 1.25 v temp. stable bandgap regulator vcc voltage error a mplifier current error a mplifier gnd icomp _ + out (-) _ + IPS20 / ips21 1 2 3 4 5 6 7 8 optocoupler current-source control 4v shunt regulator tr immed current sensing 50mv ptat 100mv temp.stable
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 3 / 12 typical feedback circuitry with control of primary flyback converter 1) current limiting: the current limiting is adjustable through risense 2) regulated voltage: the regulated voltage is adjustable through rv1 and rv2 3) compensation the voltage-control trans-conductance ope rational amplifier can be fully compensated. both of its compensation pins are directly accessible for external compensation components. the suitable compensation network is shown in fig.1. it consists of a capacitor c1 and a resistor r1in series, connected in parallel with another capacitor c2. the current-control trans-conductance operational amplifier can be fully compensated. both of its compensation pins are directly accessible for external compensation components. the suitable compensation network is shown in fig.1. it consists of a resistor r2 and a capacitor c2 in series, in parallel with a capacitor c3. resistor r4 provides the input impedance that the compensation network works with. capacitor c4, with r4, implements a small amount of filtering. determination of v out (output voltage): v out = vsense x (rv1+rv2)/ rv2 (nominal vsense = 1.19v) determination of i limit (current limit): i limit = is threshold / risense nominal is threshold : IPS20= 54mv ips21= 100mv fig. 1 u2 optocoupler out+ out- secondarygnd tx1 + c5 rv1 rv2 output + c6 vcc 1 vsense 2 vcomp 3 opto 4 gnd 8 out(-) 7 is 6 icomp 5 u1 IPS20/21 c1 r1 r3 r2 c2 risense c3 c4 l1 d1 schottky in+ in+ dc or rectified ac flyback converter r4
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 4 / 12 in-plug ? IPS20 and ips21 functional description IPS20 and ips21 are highly integrated feedback solutions for switch mode power supplies applications requiring constant voltage and c onstant current mode. they were especially d esigned to reduce the power dissipated in the load-side current sensing resistor of power supplies w ith high output current they provide precise voltage and current regulation that can be fully and independently adjusted. they source the current necessary to drive a ground- referred optocoupler connected to the line side controller. they both incorporate the same trimmed temperature compen sated 1.2v reference to set the output voltage. they only differ by the characteristics of the current sensing references. the IPS20 features a trimmed 50mv reference with a positive temperature coefficient which closely matc hes that of a pcb copper trace. this copper trace sensing method can be used inexpensively with very low associat ed power losses. the ips21 incorporates a constant 100mv reference for more conventional resistors. both the output voltage and current sense can be inde pendently adjusted through respectively rv1/rv2 and risense (fig.1) this information is presented to the i ps20/21 controller, which drives the optocoupler through the opto current-mode output pin. the shunt regulator operates like a zener diode, keeping the chip supply voltage at about 4 volts. at start-up, when the 4 volts are reached, the controller starts normal opera tion. the overall chip consumption in this case is about 600 a. if the IPS20 or ips21 vcc is connected to the convert er output voltage, then under start-up or short-circuit conditions, the IPS20/21 isn?t supplied with a high enough voltage. this is due to the fact that the chip has its power supply line in common with the power supply line of the system. therefore, the current limitation can only be ensured by the primary pwm module, that should be chosen accordingly. if the primary current limitation is considered not to be precise enough for the application, then a sufficient supply for the IPS20/21 has to be ensured under any condition. it would then be necessary to add some circuitry to supply the chip with a separate power line. the schematic in figure 3 below shows how to realize a lo w-cost power supply for the IPS20/21 (with no additional winding). please pay attention to the fact that in the par ticular case presented here, this low-cost power supply can reach voltages as high as twice the voltage of the regulated line. fig.2 output voltage versus output current
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 5 / 12 auxilliary power supply this simple circuitry allows to supply the chip with a separate power line. in case of short-circuit, when vout+ < vcc, the chip still keeps working properly and limits the output current to its maximum targeted value. derivative of aai?s patented snubber network this technique powers the feedback controller under all circumstances including short-circuits and is especially suitable for flyback, pfc and forward converters. tr1 vcc 1 vsense 2 vcomp 3 opto 4 gnd 8 out(-) 7 is 6 icomp 5 u1 IPS20/21 d1 schottky d2 + c4 + c2 r1 r2 vout+ vout- d3 c1 + c3 snubber networ k tr1 vcc 1 vsense 2 vcomp 3 opto 4 gnd 8 out(-) 7 is 6 icomp 5 u1 IPS20/21 d1 schottky d2 diode + c1 + c2 r1 r2 vout+ vout- c3 auxi l l i ary power suppl y
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 6 / 12 electrical characteristics absolute maximum rating characteristics value units ips 20 and ips21 max i cc (4v shunt regulator) 140 ma opto sourcing current with external resistor 20 ma operating junction temperature - 40 to 150 c storage temperature range - 55 to 150 lead temperature (3 mm from case for 5 sec.) 260 parameter test conditions parameters units supply, bias min. typ. max. shunt regulator voltage icc = 1 to 30 ma 3.8 4 4.2 v shunt regulator dynamic resistance (see figure 1) 1 to 50 ma - 1 3 shunt regulator max peak repetitive current - 100 - ma min i cc to ensure operation (internal current) - - 600 ? voltage regulation vsense threshold (note1) i opto = 500 a zin=10k 1.17 1.19 1.21 v vsense threshold variation with temperature i opto = 500 a, -40c to +85c (see figure 2) - +/- 3 +/- 6 mv output impedance of vcomp - 1 - k voltage gain to vcomp (see figure 7) - 115 - db unity gain bandwidth (see figure 7) - 500 - khz phase margin in unity gain - 82 - degrees vsense input current - 1.0 a transconductance from vsense to opto @ v cc = 2.5v (see figure 5) - 4 - ma / mv max opto output sourcing current without ext. resistor @ v cc = 5v (see figure 5) 1.2 - - ma max opto output sourcing current with ext. resistor @ v cc = 2.5v (see figure 3) 10 - - ma current limiting isense threshold (IPS20) i cc = 1 ma (see figure 3) 52 54 56 mv isense threshold variation with temperature (IPS20) i cc = 1 ma, -40c to +85c (see figure 3) - 0.16 - mv /c isense threshold (ips21) i cc = 1 ma (see figure 4) 97 99 101 mv isense threshold variation with temperature (ips21) i cc = 1 ma, -40c to +85c (see figure 4) - 3 - v/c output impedance of icomp - 1 - ? voltage gain to icomp (see figure 8) - 138 - db
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 7 / 12 unity gain bandwidth to icomp (see figure 8) - 2 - mhz phase margin in unity gain - 54 - degrees isense input current - -1.0 ua transconductance from isense to opto (see figure 6a & 6b) IPS20: 6a, ips21: 6b - 60 - ma/mv max opto output sourcing current without ext. resistor @ v cc = 1.30v (see figure 5) 1.2 - - ma max opto output sourcing current with ext. resistor @ v cc = 2.5v (see figure 5) 10 - - ma note1: tighter tolerances to 0.5% available upon request. note2: all values are @ 25c unless otherwise specified. note3: electrical parameters, although guarant eed, are not all 100% tested in production. figure 2: IPS20 & ips21 trimmed 1.20v reference 1.17 1.175 1.18 1.185 1.19 1.195 1.2 -40 -20 0 20 40 60 80 100 120 temp (c) vref (v) figure 1: IPS20 and ips21 4v shunt regulator icc 0 50 100 150 200 250 300 0123456 shunt voltage (v) icc (ma)
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 8 / 12 figure 4: ips21 100mv reference 97 97.5 98 98.5 99 99.5 100 -50 -30 -10 10 30 50 70 90 110 130 temperature (c) 100mv ref. (mv) figure 5: transfer function of the voltage regulation 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.185 1.186 1.187 1.188 1.189 1.19 v sense ( v ) opto current (ma) 40 45 50 55 60 65 70 -40 -20 0 20 40 60 80 100 temperature (c) 50mv reference (mv) figure 3: IPS20 ref. with coppe r temperature drift compensation
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 9 / 12 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 47.5 48 48.5 49 49.5 50 50.5 51 isense (mv) opto current (ma) figure 6a: transfer function of the IPS20 current regulation 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 98.5 98.6 98.7 98.8 98.9 99 99.1 99.2 99.3 99.4 99.5 isense (mv) opto current (ma) figure 6b: transfer function of the ips21 current regulation fig 7: open loop gain of vsense amplifier without compensation -20 0 20 40 60 80 100 120 140 0.001 0.01 0.1 1 10 100 1000 10000 100000 1000000 frequency (hz) gain (db)
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 10 / 12 application information the IPS20 and ips21 chips are intended for use as voltage feedback control and current limiting on the secondary side of switching power supplies. powering the chip (pin 1 - vcc and pin 8 - gnd) the vcc pin acts like a 4 volt zener. this is a different chip -power concept than the ips25, a self-powered feedback controller, optimized for output currents below 1a (see i ps25 datasheet for details). the gnd pin is the lowest voltage the chip sees. what this mean s is that in a typical ?positive output voltage with current sense resistor? application, the gnd pin does not go to the negative output pin of the power supply, rather it goes to the ?transformer side? of the current-sense resistor. no input vo ltage should be greater than vcc or less than gnd. it is recommended as good engineering practice to have a dec oupling capacitor from vcc-to gnd of 10uf. the intended design implementation for powering the chip is to have a r esistor from vcc to either the output voltage or a separate supply.this resistor should be sized such that at mi nimum supply voltage (and subtracting 4 volts for the vcc voltage), there is enough current to operate th e chip (3ma) plus supply the optoisolator. tips for lab experiments the IPS20/21 are fabricated in a low-voltage ic process (l ower than the ips25). this means that they can be damaged with pin voltages greater than 7 volts. when tes ting designs using an IPS20/21, it is typical to perform debug with a laboratory current-limited external power supply attached to the vcc pin. this external supply should be set for around 5 volts and 10 milliamps. it is possible to damage an IPS20/21 if one of these lab supplies is set for (say) 12 volts and 10 milliamps, the lab supply is powered-on, and then the lab supply is connected to the IPS20/21, because the vcc voltage will be 12 volts (in this exam ple) until the IPS20/21 starts conducting current and discharges any output capacitance in the lab supply. note that the overcurrent performance of a power supply using an IPS20/21 will be different based on whether the chip is powered by the output (where the vcc supply will be collapsing) versus from an independent supply. the user should be sure to check that the output voltage a nd current characteristics during overcurrent conditions meet his/her specific needs. during startup and short-circuit conditions, the IPS20/21 may not have enough supply voltage to operate. in this situation, the output current limitati on must come from the primary side pwm module, and must be designed accordingly. fig 8: open loop gain of isense amplifier without compensation -40 -20 0 20 40 60 80 100 120 140 160 0.001 0.01 0.1 1 10 100 1000 10000 100000 1000000 10000000 frequency (hz) gain (db)
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 11 / 12 vsense (pin 2), vcomp (pin 3) the internal voltage reference for vo ltage feedback is 1.19 volts. the output voltage being sensed/regulated should have a voltage divider to 1.19 volts connected to pin 2. for good voltage feedback loop performance, no capacitor should be connected from pin 2 to ground. the recommende d series-rc component values from pin 2 to pin 3 to roll-off the loop gain are 10k ohms and 68nf. opto (pin 4) the opto pin is a current source (unlike a shunt regulat or like the tl431, which is a current sink). the intended connection for the voltage feedback ne twork is to connect the opto pin to the anode of the photodiode in an optoisolator, with the cathode of the photodiode connected to ground. the IPS20/21 use ve ry little current to operate, but the user is reminded that the opto current being sourced comes through the vcc pin. icomp (pin 5) and is (pin 6) the current sense resistor connects between is and gnd. for a positive output power supply, is is the negative output pin. the internal voltage reference for current lim iting (50 millivolts for IPS20, 100 millivolts for ips21) is referenced to gnd. the recommended component values from pi n 5 to pin 6 to roll-off the loop gain are a series 10k ohms and 220pf, in parallel with 68nf. to reduce susceptab ility to noise spikes, an additional rc filter network might be desireable from is to gnd (refer to the typical application schematic figure 1 above). out(-) (pin 7) the negative side of the internal voltage reference for volta ge feedback is connected here. for a typical application with a positive output voltage and a current sense resistor, th is pin connects to the more-negative pin of the output voltage. this configuration allows th e voltage feedback to compensate for the voltage drop across the current sense resistor (which will vary with load). evaluation board there is an evaluation board (aaev2021) available for the IPS20 and ips21 feedback controllers. contact aai marketing for more details. there are also benchmark/ reference designs available that include aai flyback controllers, and application notes. package dimensions and marking the IPS20 and ips21 are available in plastic 8-pin dip and plastic 8-pin soic packages. refer to the latest version of specification aaps001 (asic advantage?s ?package number ing, marking, and outline standard?, available at www.asicadvantage.com) for specific information concer ning the package dimensions and package marking. part number/tube part number/tape&reel package temperature range IPS20c-d-g-lf ips21c-d-g-lf na 8-pin pdip 0 c to +70 c commercial IPS20i-d-g-lf ips21i-d-g-lf na 8-pin pdip -40 c to +85 c industrial IPS20c-so-g-lf ips21c-so-g-lf IPS20c-so-g-lf-tr ips21c-so-g-lf-tr 8-pin soic 0 c to +70 c commercial IPS20i-so-g-lf ipc21i-so-g-lf IPS20i-so-g-lf-tr ipc21i-so-g-lf-tr 8-pin soic -40 c to +85 c industrial
power management IPS20 and ips21 ? copyright 2006-2009 - asic advantage, inc. aads00001/aa743 - revision 5? dec 2008 12 / 12 the following is a brief overview of certain terms and conditi ons of sale of product. for a full and complete copy of all the general terms and conditions of sale, visi t our webpage http://www.asic advantage.com/terms.htm. limited warranty the product is warranted that it will conform to the applic able specifications and be free of defects for one year. buyer is responsible for selection of, use of and resu lts obtained from use of the product. buyer indemnifies and holds asic advantage, inc. harmless for claims arising out of the application of asic advantage, inc.?s products to buyer?s designs. applications described herein or in any catalogs, advertisements or other documents are for illustrative purposes only. critical applications products are not authorized for use in critical applications including aerospac e and life support applications. use of products in these applications is fully at the risk of the buyer. critical applications include any system or device whose failure to perform can result in significant injury to the user. lethal voltages lethal voltages could be present in the applications. pl ease comply with all applicable safety regulations. intellectual property rights and proprietary data asic advantage, inc. retains all intellectual property right s in the products. sale of products does not confer on buyer any license to the intellectual property. asic advant age, inc. reserves the right to make changes without notice to the products at any time. buyer agrees not to use or disclose asic advantage inc.?s proprietary information without written consent. trademarks and patents - in-plug ? is a registered trademark of asic advantage, inc. - aai?s modified snubber network is patented under the us patent # 6,233,165. in-plug ? customers are granted a royalty-free licence for its utilization, provision the parts are purchased fa ctory direct or from an authorized agent. protection for custom in-plug ? solutions when aai accepts to design and manufacture in-plug ? products to buyer?s designs or specifications, buyer has certain obligations to provide defense in a suit or proceeding claiming infringement of a patent, copyright or trademark or for misappropriation of use of any trade secrets or for unfair competition. compliance with laws buyer agrees that at all times it will comply with all applicable federal, state, municipal, and local laws, orders and regulations. buyer agrees to comply with all applicable re strictions on exports and re-e xports including obtaining any required u.s. government license, author ization, or approval. buyer shall pay any duties, levies, taxes, brokerage fees, or customs fees imposed on the products. title and delivery all shipments of goods shall be delivered exworks, sunnyvale, ca, u.s.a. title in the goods shall not pass to buyer until asic advantage, inc. has receiv ed in full all amounts owed by buyer. latest datasheet updates for the latest datasheet updates, visit our w eb page: http://www.in-pl ug.com/datasheets.htm. worldwide representatives to access aai?s list of worldwide r epresentatives , visit our web page http ://www.in-plug.com/representatives.htm copyrights copyrights and all other proprietary rights in the content rests with asic advantage inc. (aai) or its licensors. all rights in the content not expressly granted herein are reserved. except as otherwise provided, the content published on this document may be reproduced or distributed in unmodified form for personal non-commercial use only. any other use of the content, including without limitation distribution, reproduction, modification, display or transmission without the prior writt en consent of aai is strictly prohibited. all copyright and other proprietary notices shall be retained on all reproductions. asic advantage inc . 1290-b reamwood ave, sunnyvale california 94089, usa tel: (1) 408-541-8686 fax: (1) 408-541-8675 websites: http://www.in-plug.co m - http://www.asicadvantage.com

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